A critical step in integrated circuit processing is defect detection, which has multiple components. One of these components is the inspection and detection of defects at or near the wafer edge. Wafer edges can develop a number of types of defects during processing, which include but are not limited to: chips, cracks, and contamination such as resist residue. Edge defect sizes of interest may range from 1-2 microns for contamination, up to 100-500 microns or more for edge chips. These edge defects do not directly impact yield by affecting IC operation, however they can be the underlying cause of catastrophic failures. For example, if a wafer edge is chipped or cracked, subsequent exposure to high-temperature processing steps such as Rapid Thermal Processing (RTP) or Chemical Vapor Deposition (CVD) can cause the wafer to shatter. This can result in, not only the loss of that particular wafer, but contamination of the other wafers in the process chamber, as well as contamination of the equipment, which is costly and time-consuming to clean up. Thus, effective edge inspection and defect detection can have great importance in optimizing yield and throughput of wafers.
Since the edge defects do not directly cause yield loss, as described above, the calculation for Return on Investment (ROI) for edge inspection systems is complicated. Edge defects may be infrequent, thus requiring 100% inspection of each wafer in order to detect process control problems. Therefore, a high-throughput, low-cost edge inspection system is required in order to provide a favorable ROI.
FIG. 1 illustrates and defines the wafer regions in the edge vicinity, for a 300 mm diameter wafer. Frontside 100 and backside 110 of wafer 120 include Fixed Quality Area (FQA) 125, Edge Exclusion (EE) region 127 of width 2-3 mm, including top near edge region 130 and bottom near edge region 140, top bevel 150, and bottom bevel 160, each encompassing about 0.5 mm radial dimension. Apex 170 has a vertical dimension of about 0.5 mm. Note that the illustration shows an ideal profile: actual wafer profiles in the edge vicinity may be a continuous curve or have rounded corners, rather than having distinct planar bevel and apex regions as shown.
Several edge inspection systems are currently being marketed, for example by Raytex, Honda Electron, and EVG. The Raytex system is described in U.S. Pat. No. 6,798,503, issued Sep. 28, 2004. The Honda Electron system is described is US Patent Application Publication No. US2003/0169916 μl, published on Sep. 11, 2003. In general, these available systems utilize multiple sensors and/or cameras at different positions to inspect the top (130) and bottom (140) wafer surfaces as well as the bevel (150, 160) and apex (170) regions. By way of example, Honda Electron and EVG use multiple cameras positioned to separately image the top (130), bottom (140), and bevel (150,160) regions. Another system, manufactured by Raytex, uses a laser source directed at the wafer apex, and an elliptical mirror where the apex is at a first focus, and scattered light is collected at the second focus. The scattering flags potentially defective areas, which are then imaged by additional cameras to reject false positives and nuisance-type defects. For example, small contaminating particles may not be of interest to a customer, but may scatter sufficient light to trigger the laser scattering apparatus. These “nuisance” defects need to be identified and filtered out so as not to overwhelm the user with a large number of them.
The use of multiple cameras yields bulky inspection systems and also increases the system cost. It also requires multiple high-speed interfaces to capture the acquired images into computer memory, which also increases the cost of multiple cameras.
An edge inspection system providing simultaneous inspection of multiple edge vicinity regions selected from: top 130 and bottom 140 near-edge, apex 170, and bevel 150, 160 regions, projected in piecewise fashion onto a linear sensor array, preferably with a single camera in a compact head, would be highly advantageous, both in reducing cost, and in enabling integration to a front-end wafer handler.